Time assignment speech interpolation system



March 1967 D. I. URQUHART-PULLEN 3,311,707

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March 28, 1967 D. l. URQUHART-PULLEN 3,311,797

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SPEECH TO RECEIVE PULSE DISERM. STORE A March 28, 1967 I D. 1.URQUHART-PULLEN 3,311,707

TIME ASSIGNMENT SPEECH INTERPOLATION SYSTEM Filed June 26, 1965 8Sheets-Sheet 8 FROM UIREUITZ 5H1 1 REBEIVED [JLSIGNALS F RAME A 7 lLSTEFGENERATOR J FROM STORM United States Patent M 3,311,707 TIME ASSIGNlWENTSPEECH IN'IERPOLATION SYSTEM David Ian Urquhart-Pullen, Ascot, England,assiguor to Associated Electrical Industries Limited, London, England, aBritish company Filed June 26, 1963, Ser. No. 290,797 Claims priority,application Great Britain, June 27, 1962, 24,722/ 62 Claims. (Cl.179-15) This invention relates to time division multiplex transmissionsystems in which signals of a number of independent information channelsare transmitted over a single transmission path in a recurrent sequence.

The invention is applicable both to telephone systems for transmitttingspeech signals and also to systems transmitting information other thantelephone signals such, for example, as video signals and data signals,e.g. in telemetry. It is applicable to transmission over lines and alsoto transmission over radio links.

The invention is especially applicable to transmission systems of thekind in which a burst of information, i.e. a train of pulses of eachinformation channel, is transmitted in turn and is to be distinguishedfrom systems in which single pulses of each information channel aretransmitted in turn.

Such transmission systems may include storage means at the transmitterinto which the signals of a number of channels can be writtenrecurrently and then read out in bursts or trains for transmission tothe receiver which is provided with a complementary arrangement fordistributing signals to the respective receivers, such for example asthe systems described in co-pending U.S. applications No. 833,020 newPatent No. 3,084,222 and No. 206,808 now Patent No. 3,213,201.

It is well known that in multiplex transmission it is not necessary toprovide as many transmission channels between a transmitter and areceiver as there are information channels as it is unlikely that peoplewill wish to transmit on all the information channels at the same time.

However if there are fewer transmission channels than informationchannels the problem arises of selecting which information channels areto be transmitted at any time.

The present invention comprises a multiplex transmission system providedwith a transmitter having signal storage means into which signals from aplurality of information channels are fed in recurrent cycles, and fromwhich signals are read and transmitted in the intervening alternatecycles. Channel selection means having information storage means, areprovided with means for interrogating the signals of each informationchannel in the signal storage means. The information storage means areeach provided with two devicesthe first of which is set if the channelcarries information during the present cycle, which in turn sets thesecond device which retains its setting until the next cycle. When bothdevices are in the set state, the signals of the associated informationchannel are transmitted.

Preferably the storage means includes separate Zones for each channeland information is fed recurrently to each zone, the contents of eachzone is then transmitted as a short train of information pulses.

The condition of each information channel may be compared with itscondition during the previous cycle and priority for transmission isgiven to channels having information during successive cycles.

According to one embodiment of the invention there is provided a queuecounter having a number of stages corresponding to the number oftransmission channels, means for interrogating the storage zone forstepping the 3,3ll,707 Patented Mar. 28, 1967 counter or stage for eachzone having information during two successive cycles and means wherebythe counter is then stepped on through its remaining stages and pulsesare fed back to activate a further information channel for transmissionfor each unfilled queue counter stage, the channels activated beingthose containing information during the current frame.

In order that the invention may be more clearly understood referencewill now be made to the accompanying drawings, in which:

FIG. 1 explains the comb system of transmission,

FIG. 2 shows diagrammatically the arrangement of the store matrix at thetransmitter,

FIG. 3 shows in block form the store switching arrangement at thetransmitter,

FlG. 4 similarly shows the store switching arrangement at the receiver,

FIG. 5 shows for purposes of explanation a modified arrangement of astore matrix having four rows and four columns,

FIG. 6 shows a switching sequence for a modified arrangement in whichwriting and reading are carried out with line interlace,

FIG. 7 shows the general arrangement of time assignment apparatus foruse with the transmission apparatus of FIG. 3,

FIG. 8 shows the switching circuit for applying deflection voltages tothe storage devices,

FIGS, 9 and 9A show graphically the voltage changes occurring in thecircuit of FIG. 8,

FIG. 10 shows the queue control circuit,

FIG. 11 shows the busy channel marker circuit,

FIG. 12 shows the channel information pulse generator,

FIG. 13 shows the receive store control circuit, and

FIG. 14 shows the TASI circuit at the receiver schematically.

The arrangement to be described is one in which information channelpulses are grouped together in short pulse trains for transmission, thepulse trains belonging to different information channels beinginterleaved, and recurrent cycles of such interleaved pulse trains beingtransmitted to a receiver where the pulse trains are distributed torespective demodulators. This method of time division multiplexing isoften referred to as comb transmission as distinct from slottransmission in which individual T.D.M. pulses from each transmissionchannel are interleaved and transmitted in recurring cycles. Combtransmission has the advantage over slot transmission that, other thingsbeing equal, the bandwidth required for comb transmission is less thanthat required for slot transmission since with comb transmissioncross-talk is restricted to that occurring between successive trains ofpulses, whereas slot transmission is susceptible to crosstalk betweenany successive pair of pulses since these will always be of differentchannels.

It is a well known fact that it is not necessary to provide atransmission channel between the transmitter and the receiver for thefull number of information channels which are fed to the transmitter andfed from the receiver since it is unlikely that everybody will want tospeak at the same time, and systems providing fewer transmission thaninformation signals are known as Time Assignment Speech InterpolationSystems, referred to as T.A.S.I. for short. The arrangement to bedescribed concerns the application of T.A.S.I. to a comb transmissionsystem, and for the purposes of explanation, a transmitting andreceiving system has been assumed in which there are 16 informationchannels and only 8 transmission channels. It is to be appreciatedhowever, that this is by way of example only and that the principlesdescribed are applicable to considerably more information andtransmission channels. With such systems it is necessary to providemeans for selecting for transmission, information channels that arebusy, i.e. actually carrying speech or like signals, up to 8 in numberat any time, and for transmitting these signals with suitableidentification signals to indicate to the receiver the informationchannels to which the transmitted speech signals belong.

Referring to the drawings, FIG. 1 shows for purposes of comparison fourcycles a, b, c, d of a 16 channel time division multiplex transmission.The row A illustrates slot transmission, the row B comb transmission andthe row C illustrates comb transmission with T.A.S.I. and indicates themethod of inserting the identification signals between trains of channelsignals. It will be observed that the application of T.A.S.I. to thesimple comb transmission shown in row B has resulted in the pulse trainsbeing more widely spaced, this enables a correspondingly reducedbandwidth to serve for transmission without degradation of thecross-talk factor. It will be appreciated, of course, that where agreater bandwidth is available, the pulse trains could be compressed intime so as to permit a greater number of channels to be transmitted fora given cross-talk factor than would otherwise be possible.

Slot to comb conversion can be effected in a number of ways, the exampledescribed herein is of the kind described in co-pending US. applicationNo. 833,020 employing storage matrices at the transmitter and receiver.In the following description it will, for convenience be assumed that atthe transmitter writing will be carried out in columns and reading inrows and at the receiver writing effected in rows and reading incolumns. It will be understood, however, that converse arrangementscould equally well be employed and of course that rectangular matricesis only one example of application.

FIG. 2 shows the arrangement of a raster at the transmitter in which, asabove mentioned, it is assumed that writing is carried out in verticalsweeps down each of the columns in turn passing from left to right.During writing sample signals from each of the sources are Written inturn into the store, the writing being sequentially downwards and thedisplacement between samples being uniform so that in each row of theraster all the signals will be associated with the same channel.

The writing of a column is followed by reading of a row in which thestorage tube is scanned horizontally as shown in FIG. 2. Reading andwriting alternate in a manner which will be described subsequently.Since each row contains signals of the same channel the result will bethat a short train of signals from each of the channels in turn will betransmitted, and thus slot to comb conversion is achieved.

FIG. 3 shows in block form the store switching arrangement at thetransmitter. Half the input information channels, i.e. channels 1-8 inthe example considered, are fed through associated end gates on the leftof the figure and Gate G1 to store A, the send gates being operatedsequentially so that each information channel in turn is connected tothe store. Similarly the remaining information channels, i.e. channels 9to 16, are connected through send gates and gate G2 with store B. StoresA and B read and write alternately during successive line scans and arecontrolled by the gates G1, G2, G3 and G4. Control signals A and B areapplied alternately to the gates so that opening of gates G1 and G4alternates with G2 and G3. When G1 and G4 are open during one line scana column of incoming signals is fed through gate G1 and written intostore A. At the same time a row of signals in store B is read and fedthrough the gate G4 to the transmission path. At the end of the linescan, signal A is removed and signal B applied. Gates G3 and G2 will nowbe opened and G1 and G4 blocked. Thus a row of information in store Awill be read out and transmitted while at the same time a column ofinformation is being written into store B.

FIG. 4 shows the corresponding arrangement at the receiver whichoperates in a similar manner, but in this case since information channeldistribution and not selection is involved, each store need accommodateonly four transmission channels. Thus, store C is associated withtransmission channels 1 to 4 and store D with transmission channels 5 to8. The incoming signals are fed alternately into store C and store D,whilst information is being written into store C and information isbeing read out from store D and passed through the appropriate receivergates associated with the respective channels. The control is obtainedby means of signals A and B which control the gates G5, G6, G7 and G8.The signals A and B are approximately synchronised with signals A and Bat the transmitter and it follows that, with the arrangement shown eachtransmitter store will always transmit signals to the same receiverstore.

An important advantage of the proposed arrangement is the reduction ofnoise in the transmission and this is achieved by so arranging thetransmitter and receiver that the same channels always are written on tothe same store, this avoids the noise caused by switching from one storeto the other such as is liable to occur if the writing occurs frame byframe.

FIG. 5 shows a transmitting matrix employing four columns and eight rowsfor the purposes of explanation. It will be observed that the columnsare designated by small letters representing the pulse cycles, and therows by numerals designating the information channels.

In the T.A.S.I. system to be described, a row is scanned only if thecorresponding information channel is busy, and not more than four rowsmay be scanned during any frame, the rows corresponding to quiescentinformation channels being skipped in the scanning process.

FIG. 6 shows the sequence of switching which would be carried out in thecase, for example, of information channels 1, 3, 4, 6, 9, 10, 13 and 15being busy, the remaining channels being quiescent for the time being.

In FIG. 6, a column is written into store A, information signals beingstored in the a storage elements 111, 3a, 4a and 6a, the remaining astorage elements of Store A being empty. At the same time, a busy row ofpreviously stored information is read out from Store B. In order,however, that the reading scan shall not try to read a store positionbefore any information has been written into it, it is necessary tostagger the reading so that the reading of a row commences at the columnfollowing that column which has just been written and finishes up at thecolumn which has just been written.

To perform the T.A.S.I. operation described above, it is necessary tosample the lines to ascertain which information channels are carryingspeech and in the actual arrangement to be described the sampling iseffected by investigating the first column during writing. It is alsonecessary to generate channel information pulses to indicate which ofthe information channels are being transmitted at any time, and asindicated in FIG. 1, these pulses are generated in pairs and inserted ingaps between adjacent trains of speech channel pulses. To avoid thisarrangement causing difficulty due to a speech train being transmittedin advance of the corresponding information pulse, it is arranged thatthe information pulses received during one frame are stored at thereceiver and utilised for the subsequent frame.

Referring now to FIG. 7, which shows the general arrangement of theT.A.S.I. apparatus, signals from the information channels (senders) arefed in at the left hand side in slot formation, i.e. as in FIG. 1A. Theinformation channel pulses are fed alternately to stores A and B wherethey are written according to the matrix shown in FIG. 2. At the sametime the pulses are fed in turn through a gate GA to a speech detectorwhich during the first column of writing of a raster samples eachinformation channel and passes a pulse to the queue controller if itreceives a signal from the channel concerned. A sampling A pulse X,which lasts throughout the first column of writing on both stores, i.e.for the duration of a full pulse cycle such as a FIG. 1, is applied toopen the gate GA for the duration of the first Writing column only.

In the queue control circuit the busy information channels in thepresent frame as shown by the signals from the speech detector arecompared with those in the previous frame so as to ensure that thechannels which are registered as busy in both the previous and presentframes have priority in the allocation of a transmission channel overother information channels which have become busy after having beeninactive in the previous frame. This arrangement minimises thepossibility of speech being cut-off by the T.A.S.I. circuit. Otherwise,free transmission channels are allocated in the order of reading theinformation channels into the main stores.

From the queue control circuit, information is passed over separateleads for each channel to the busy channel markers and to the channelinformation generator. Each busy channel marker contains a markingelement for each channel served by its associated main store, i.e. A orB. Thus the busy channel marker for Store A is associated with one halfof the queue control circuit, while the busy channel marker for store Bis associated with the other half of the queue control circuit. The busychannel markers operate in conjunction with the queue controller tocontrol the Y shift of the appropriate store so as to select the rowcontaining the next busy channel to be read out onto the outgoingtransmission line. The function of the channel information generator isto send out signals regarding the identity of the transmittedinformation channels, these being generated, in batches, i.e. pairs inthe present example, and transmitted between the speech pulse trains. Inthis arrangement, the input gates A and B are controlled by clock pulsesfrom a central timing control and referred to as write P" pulses 1-8 and9-16 respectively, While the output gates A and B are controlled by readP pulses 2-5 and -13 respectively, the read P pulses being displacedfrom the write P pulses by half a cycle period. Thus while informationchannels 9-16 are being written into store B, information signals arebeing read out from store A on to transmission channels 1-4, the latterbeing effected in time periods 2-5, similarly when channels 1-8 arebeing written into store A, information signals are being read out fromstore B on to transmission channels 5-8 in time periods 10-13. Thistiming of the transmission channels ensures the requisite gaps in thetransmitted signal trains and isolates the stores from the highway whileinformation is being written into them.

FIG. 8 shows, for store A only, the control circuit in block form forcontrolling the deflection system of the store. At the top left handcorner, LE1 is a line binary counter which operates the gates G1 and G2alternately. The line synchronising pulse recurrence frequency is anexact sub-multiple of the multiplex rate and occurs at the. start ofeach writing line scan. The line and frame synchronising pulses are alsopassed to a frame discriminating circuit which separates out the framesynchronising pulses and uses them to reset 5G3. Unmodulated multiplex Ppulses are fed to the gate G1, to the T.A.S.I. circuits and to a readpulse distributing chain RD.

FIG. 9 shows graphically the voltage changes occurring in FIG. 8 for the16/8 channel system being described. The numerals in circles in FIG. 8refer to the graphs in FIG. 9 as showing the voltage changes at thesepoints.

In FIG. 9 it is assumed that horizontal reading sweeps and verticalwriting sweeps alternate.

With the line binary circuit LE1 set to its 0 state, the linesynchronizing pulse passes over the 0 output lead and triggers the stepgenerator 563 which produces on its output lead the bias waveform 3.Multiplex pulses are applied to the cyclic counter RD and pulses 2-5 arepassed by gate G2 to step generator 8G2 which produces waveform 4 on itsoutput lead. This controls the horizontal sweeps along rows selected bythe deflections. The

outputs from step generators SG2 and 8G3 are combined in the adding gateG3 to produce the composite waveform 5, which is fed to the X2deflection plate and also to the schmidt trigger circuit. This lattercircuit is arranged to trigger at the level indicated by the dotted linein graph 5. The output of the schmidt circuit is shown in Graph 6 andthis is applied to the X1 deflection plates. The resultant deflectionproduced is indicated in Graph 7, which gives the staggered read scanrequired. The output 2-5 from the counter RD is also fed to the A storeread gate B shown in FIG. 7 so that any output from the main store otherthan that at these times is prevented from reaching the transmissionhighway.

When the line binary LBl is set to its 1 state, gate G2 is inhibited andgate G1 is primed to pass the multiplex pulses to the step generator SG1which produces the step waveform shown in Graph 8. This controls thevertical deflection. The line synchronizing pulse is also passed to theT.A.S.I. circuit which produces bias output levels which are applied tothe Y plates during the horizontal sweeps and select the rows containinginformation channels selected for transmission. For the purposes ofexplanation, it will be assumed that of the information channels 1-8served by store A channels 1, 3', 4 and 6 are busy and have beenselected for transmission. The process of selection will be described infull below, when the T.A.S.I. circuits are considered in detail. Theresult is that the levels 1, 3, 4-, 6 shown in Graph 9 are applied inturn to the Y2 deflection plate, and the resultant waveform appliedbetween plates Y1 and Y2 is shown in Graph 10 which shows that aftereach vertical writing scan, the Y deflection is successively positionedon rows 1, 3, 4 and 6, in readiness for the reading scan.

The store control circuit for store B is the same as for store Adescribed above, with the exception that the X and Y scans are reversedin time. This may be achieved by simply reversing the output connectionsfrom the line binary gate, so that while store A is being written into,store B is being read, and vice versa.

FIGS. 10, 11 and 12 show the T.A.S.I. circuits in logical detail. FIG.10 shows the queue control circuit, FIG. 11 shows the busy channelmarker circuit while FIG. 12 shows the channel information pulsegenerator.

Referring to the queue control circuit of FIG. 10, with the exception ofthe counter CQ the speech detector and the gates GA and GX which arecommon to all channels of both stores, the equipment shown is associatedwith one information channel only, i.e. channel 1. The suflix numeralshown with the component designations in this equipment refers to thechannel with which the equipment is associated, i.e. BMAI belongs tochannel 1, while channel 2 has a separate bistable element BMA2 etc.(not shown in the drawing).

For each information channel a pair of stores BMA and BMB is provided.These comprise simple bistable elements. Each BMA store has its inputcoupled to the output from the speech detector over a distributing gateG1. Each of these distributing gates is primed by a different successivemultiplex P pulse, so that the gates are opened sequentially by theincoming T.D.M. channel slots. Between the BMAl and BMBI stores is a setof three gates GA1, GCl, GD The gate GA1 is a selecting gate. It is openwhen BMAl is set, i.e. is in the 1 state, and allows a pulse from thecounter CQ to set BMB1 to the 1 state. Thus BMBl will act as a memorystore and have the same state that BMA 1 had during the previous frameirrespective of the state of BMAl during the present frame as describedmore fully below. The gates Gill and GDl which are NOT gates aresearching gates forming a chain with the corresponding searching gatesbelonging to other channels. These gates are controlled by the counterchain CQ which is common to all channels, and the operation of thecircuit is as follows.

Assume initially that the BMB stores are set up with a number, up to 8,of busy channels. Therefore the BMB 7 storage elements corresponding tothe busy channels will be in the 1 or set state and all the other BMBstores will be in the 0 or reset state. This is the state of affairswhich can exist at the end of a frame period. During the first writingline scan of the new frame period the BMA memory units are set upaccording to the information from the speech detector. The separate busychannel pulses set the corresponding BMA storage elements and are alsopassed to counter CQ, via gates GM. These gates are primed by the BMBstores, so that the counter CQ only steps when both BMA1 and BMBI areset. Therefore, considering channel 1, at the end of the first writingline, scan memory BMA1 can store busy information relating to thepresent state of channel 1, BMBl contains busy information relating tothe previous state of channel 1, and CQ contains comparative informationabout channel state changes. The output of CQ is blocked off during thissetting up scan by pulse x applied to gate GX. Pulse x is of the sameduration as the line scan and can be generated in the store-scanwaveform generating equipment to occur during the first writing linescan.

The first line sync pulse of the next line period, i.e. pulse p1 is usedto reset memory store BMBl. Only those units are reset to zero in whichthe speech channel has become vacant. Gates GB ensure that this rule isfollowed, as they only permit the reset pulse to reach the associatedBMB store if its corresponding BMA unit is reset, i.e. in the 0 state.As pulse x has now vanished, the input of counter CQ is connected to themultiplex pulses and its output through GX to the memory chain. If therehas been a change of channel state since the last frame, CQ will nothave stepped its m positions, and the multiplex pulses will be able tostep it on until stage m is reached. Each step produces an output pulsewhich is fed via GX to the selecting and searching gates of the memorystores BMB.

Suppose that channel 1 was busy in the previous frame and is unchanged.BMA1 will be set and so will BMBI. Gate GA1 will be open, butineffective as BMBl has already been set, GC1 will be shut due to theinhibit 1 from BMAL and GD1 will be open. Therefore, the pulse from CQ(if there is one) will pass through GD1 to the second stage, L1 beingconnected to the upper sides of GC2 and GDZ, it being assumed thatsuccessive stages are identical with the stage shown. Assume both BMA2and BMB2 are off. In this case gate GAZ is shut, GC2 is open and GD2 isshut. Therefore, the pulse passes through this stage without affectingit, via gate GC2 to the next stage. In the third stage assume that thespeech channel has changed from busy to vacant. BMA3 will be reset, i.e.in the 0 state, and BMB3 will also be reset, i.e. in the 0 state, as thereset pulse will have reset it from its previous on state. Therefore theCQ pulse continues via GC3 to the fourth stage. Assume that channel 4has become busy, whereas previously it was vacant, BMA4 will be set andBMB4 will be reset. S0 gate GA4 is open, GC4 is shut and GD4 is shut.The CQ pulse is diverted from the main line by GA4 and triggers BMB4into the set state. This action opens gate GD4 so that a second CQ pulsecould pass on the stage 5 and any remaining CQ counter output pulses canset up any remaining BMB units to a total of m units maximum. After themth CQ pulse, the chain counter is saturated and cannot produce any morepulses until it is reset by the frame pulse. This frame pulse alsoresets the BMA units ready to receive the next train of channel statepulses from the speech detector.

As described earlier, the Queue Controller can only discriminate for oneframe period at a time, however, it will be apparent that thisdiscrimination could be extended by the incorporation of an additionalmemory chain for each additional frame period to be remembered.

Referring now to the busy channel marker circuit of FIG. 11, thefunction of this circuit is to feed out the appropriate bias voltage tothe Y2 plate of the Y deflection system of the main store at the startof each reading line scan. Thus if channel No. 2 is the first busychannel during a frame period, the busy channel marker must feed outvoltage level 2 to the Y deflection system.

In FIG. 11, only the equipment for one channel has been shown. The gatesGS, GP and GQ are selecting and searching gates similar to the gates GA,GC and GD in FIG. 10, the gates GP and GQ for each channel beingserially connected in pairs to form a chain.

It will be observed that there is a connection from the one side ofstore BMBl of FIG. 10 to the gate GS1 of FIG. 11. Similar connectionsexist between the one side of the BMB stores for other channels and thecorresponding GS gates not shown.

There is a separate Busy Channel marker circuit as shown in FIG. 11 foreach information channel and each has its gate GS connected to itsassociated queue control store BMBl-BMB16. The busy channel markercircuits each serve to apply an appropriate deflection to the Y2deflection plate of its associated transmitting store. It will berecalled that by the time the first P1 pulse of the reading line scan iscompleted, the earliest busy channel to be transmitted has had its BMBmemory set to the one state. At the beginning of the first read pulsethe busy channel marker locates this channel and applies the appropriateY2 voltage to the Y deflection system. The P2 pulses at the start ofeach line scan are applied to prime the gates GS. Assume the firstchannel has been marked busy from the queue control circuit an operatingsignal will be applied from the store BMBl to open gate GSl and allowthe next pulse to set the bistable switch BS1 to its one state. Thisoperates gate GV1 to apply Level 1 to the deflection plate Y2. Thesignal from BMBl also inhibits the gate GPI. The gate GQl which wasclosed while the switch BS1 was in its 0 condition, is primed by theswitch BS1 in its one condition in readiness for the next line scanpulse. Although the gates GS associated with other busy channels willalso have received input signals from their associaed BMB stores, thesegates are not primed by the applied P2 pulse since the gates GPI and GQIwere both closed during receipt of this pulse and hence its passagebeyond the first stage was blocked. At the next line scan however, thegate GQl will already be primed by the signal from switch BS1 now in itsone state, and consequently the P2 pulse will pass via GQl to the nextstage. Assume now that channel 2 is inactive, i.e. BMBZ is in its 0condition. In this case, there is no signal to operate gate GS2, but GPZwill be primed since there is no inhibition signal from the BMB2 store.Consequently the P2 pulse is able to pass through the second busy markerstage and will in fact, progress along the chain of GP and GQ gatingpairs until the next busy channel is encountered when the GS gate ofthat channel will be opened and the corresponding BS switch actuated tobring about the application of the appropriate voltage level to the Y2deflection plates. This action continues for each line scan of the frameuntil all the busy channels have been transmitted.

Referring now to FIG. 12,,the channel information pulse generator willnow be described. It will be recalled that the function of this circuitis to transmit pulse signals to indicate at the receiver the identity ofthe channels being transmitted, these signals being transmitted inbatches between the pulse trains transmitted from the transmittingstores. In the particular example being c oT1- sidered the channelinformation signals are transmitted by pairs of pulses according to acode and the scheme adopted employs a full height pulse to denote a busychannel and a half height pulse to denote an inactive channel, positivepulses to denote line periods and a negative pulse to denote the end ofa frame. Of the equipment shown in FIG. 12, the gate G01 and the pulseshaping circuit are provided for information channel 1 only, similargates and pulse shaping circuits are provided for the remaininginformation channels, these not being shown. The

counter QR and gates GS and GR are common for all information channels.The operation of the circuit is as follows.

At the end of the first reading line period, pulse p,, triggers thecounter to its first output position which primes gate G01. If thebistable circuit BMB1 is set showing that channel 1 is busy, gate G01 isalso primed by this output. So pulse p can pass through gate G01 on tothe common output lead. However, if BMB1 is in its condition, (i.e.channel 1 is vacant) gate G01 remains shut, and pulse p,, cannot getthrough. Instead, an attenuated p pulse is fed onto the common lead viathe shaping network. Because a busy pulse from the counter GR is ofgreater amplitude than a vacant pulse, there is no need to gate thevacant pulses as they will be swamped whenever a busy pulse is passed onto the common lead. The pulses p etc. are fed to the gates GO inaccordance with the number of Cl. pulses in each transmitted batch.

In the system proposed, the frame synchronising pulse is of reversepolarity. Therefore a polarity-reversal circuit in inserted between thepositional pulse common lead and the transmission line. This circuit isactuated by the final pulse of the chain counter. When the counterreaches its final position it primes gate GO and at the same timeswitches the P-pulse common lead from direct connection to thetransmission line to connection via a minus-one amplifier. This reversalis achieved by means of the simple two gate system shown in FIG. 12 inwhich gate GR is normally open but gate GS is opened to pass the pulsesthrough the amplifier. The next pulse into the counter switches it backto position 1, which switches out the minus-one amplifier by cutting outgate GS and priming gate GR and makes the pulse polarity revert tonormal again.

Turning now to the apparatus for T.A.S.I. reception, as explained abovethe main receiving stores need accommodate only the transmitted channelsand consequently in the present example each receiving store is arrangedto store only 4 channels each at any one time. It is also arranged inthe present example that writing into the received stores is effectedhorizontally and reading, vertically. The writing scans are staggeredwith respect to one another. This results in a receive store controlcircuit which is very similar to the transmit store control circuit. Inthe receive store control circuit however, although no Y deflection isno longer dependent upon channel activity, the start of each Y scan hasto be controlled since the time for which the Y scan remains at eachstep during the read-out process is dependent upon channel activity.

The function of the receiving apparatus, it will be recalled, is torestore the incoming time assigned channel comb signals to theiroriginal non time assigned T.D.M. slot signals. Thus, for example, if atthe transmitting end the information channels 1 and 3 are busy, then atthe receiver in the process of restoring the transmitted comb signalsfor channels 1 and 3 to the original slot formation, a gap of one timeslot must, during reading, be inserted between the time slots read fromthe main store for channels 1 and 3.

FIG. 13 shows the receive store control circuit for store 1 only. Theline pulse discriminator feeds line synchronizing pulses to the linebinary counter RLBI. In its 0 condition this counter applies a signal toset the step generator RSG3 and the gate RG2 is primed due to theabsence of an inhibit signal from the one output of the counter and thisgate passes pulses at times p2 to p5 from the counter RRD, causing thestep generator RSG2 to step at these times. The step generators RSG2 andRSG3, the adder and the gates RG1 and RG2 operate in the same way asdescribed above in connection with the send store control circuit ofFIG. 8 and the waveforms produced are the same as those shown in FIG. 9,Graphs 3, 4, 5, 6 and 7. The gate RG4 is also primed at this time andpasses the waveform shown in FIG. 9A, Graph 1 to the Y2 plate of thedeflection system. When the binary counter RLB1 changes to its onecondition the gate RG2 is closed and RG1 opened, allowing the multiplexpulses to pass to the step generator RSGl. This corresponds to the stepgenerator SGl of FIG. 8, but instead of producing a regularly steppedwaveform as in FIG. 9, Graph 8, it has an over-riding control exertedupon it from the receive T.A.S.I. circuit, which causes the stepping tobe restricted to only four steps, corresponding to the four informationchannels stored in the associated receiving store, and the duration ofeach step to be determined by the channel activity as indicated by thereceived channel information pulses. For example, Graph 2 of FIG. 9Ashows the composite waveform that would be applied to the Y deflectionplates in the case where channels 1, 3, 4 and 6 are indicated as busy.Thus at the start of a line scan the first storage element of a columnis scanned for two multiplex time periods, at the end of which thesecond storage element is scanned for one multiplex time periodwhereupon the third storage element is scanned for two multiplex timeperiods when the fourth storage element is scanned for a period of threemultiplex time periods. The output signals thus reproduced by the storeare applied to a gate GL (FIG. 14) also controlled by the T.A.S.I.circuit to terminate each such reproduced pulse at the end of its propermultiplex time period, thus inserting the required time gaps between thenon-adjacent busy channels.

It will be appreciated that the individual information receivers will beconnected to the circuit in a recurrent sequence under the control ofthe multiplex pulses which are synchronised with those at the receiver.The purpose of the time gaps is to ensure that the information is fedout at the instant when the correct information receiver is connectedup. This result is achieved by the T.A.S.I. circuit.

FIG. 14 shows the receive T.A.S.I. circuit in schematic form. Thecomponents EH1, GHl and Gil are for one information channel only and arerepeated for each .information channel. The parts in the dash linerectangles are common to all the channels but are only concerned withone store and are repeated for the other store.

Channel information pulses fed into the gate GF which is opened by framepulse A and gate GF2 of the next circuit by frame pulse B. The framepulses are generated by a binary counter triggered from the framesynchronising pulses. It is necessary to have A and B frame periods asthe Channel Information pulses transmitted during any frame period arenot used until the following frame period when they will be associatedwith the stored channel signals also transmitted during the previousframe. Therefore the channel information pulse memory units (bistablecircuits EH1 etc.) are filled up during frame A and read out duringframe B. An equivalent circuit associated with receive store 2 is filledup during frame B and read out during frame A.

Assuming that gate GP is open, the channel information pulses feed intogates 6H1 to GHn and to counter CA. CA switches to output 1 at thearrival of channel information pulse 1 and gate GHl opens so thatchannel information pulse 1 passes to bistable unit BHI. The bistableunits are arranged such that they only switch on if the incoming channelinformation pulse is of more than half its maximum amplitude, i.e.indicating a busy channel. Thus, at the end of the first line scanperiod, iz/m=2 in the present example) bistable units will have beenpresented with either busy or vacant pulses and will have switched on orremained off accordingly. At the end of frame period 1, all the memoryunits EH1 to BHn will have been set up and gate GF shuts, as frame pulse1 collapses.

Now frame pulse B appears and opens gate GK. The multiplex pulsesimmediately start triggering counter CB. The outputs from CB areconnected to gates GJl-Gln which connect the outputs of BH1BHn to thecommon output line. As CB counts in synchronism with the multiplexpulses, pulses or gaps will appear on the common line to gate GL.Therefore gate GL will open every time a busy channel is read by thestore, and shut during the pause periods when the store is standing atvacant channel positions.

The common line horn GJl-GJn is also connected to gate GY, which passesmultiplex pulses through to the Y scan step-generator. Thestep-generator steps every time a multiplex pulse is presented to it.The application of the multiplex pulses is, however, controlled by gateGY such that they are only applied to the step generator for a busychannel position. The connections to the receivers will continue to bestepped during the gaps until the receiver associated with the next busychannel is reached when gate GL will open and information be passed.

At the end of frame period B all the bistable units BI-Il-n are reset bythe frame pulse ready to be filled with fresh information by theincoming C.I. pulses. The counter CA is also reset ready to count downagain. The identical equipment associated receive store 2 operates tothe alternate frame periods, with all the frame A and frame B pulsesinterchanged. After having been set up as described above, thecommon-line equivalent to the output of GJl-n operates a gate inparallel with GY. Therefore, the multiplex pulses can step the samestepgenerator during each frame period. A similar gate in parallel withGL is operated by the same common line and connects the store output tothe output line. Thus, the step generator for the Y scan continuouslysteps in accordance with the incoming T.A.S.I. instructions.

It will be appreciated that a station having this equipment will operatein conjunction with a corresponding distant station. Thus, the nearstation will comprise both a transmitter and also a receiver operatingwith a receiver and transmitter respectively at the distant station.

What I claim is:

l. Ina multiplex transmission system having a smaller number oftransmission channels than information channels, a transmitter, signalstorage means in said transmitter, means for writing signals from eachof the information channels into the store in recurrent cycles and meansfor reading from the store information to be transmitted during theintervals between the writing cycles, together with channel selectionmeans including means for interrogating each channel during writing, afirst device which is set if the channel carries information during thepresent cycle, a second device which is set by the first device andretains its setting until the next cycle and means for reading from thestore signals of those information channels whereof both associateddevices are in the set state.

2. In a multiplex transmission system having a smaller number oftransmission channels than information channels, a transmitter, signalstorage means in said transmitter, means for writing signals from eachof the information channels into the store in recurrent cycles and meansfor reading from the store information to be transmitted during theintervals between the writing cycles, together with channel selectionmeans including means for interrogating each channel during writing, afirst device which is set if the channel carries information during thepresent cycle, a second device which is set by the first device andretains its setting until the next cycle and means for reading from thestore signals of those information channels whereof both associateddevices are in the set state.

3. In a multiplex transmission system having a smaller number oftransmission channels than information channels, a transmitter, signalstorage means in said transmitter, means for writing signals from eachof the in formation channels into the store in recurrent cycles, andmeans for reading from the store information to be transmitted duringthe intervals between the writing cycles, together with channelselection means including means for interrogating each channel duringwriting, a first device which is set if the channel carries informationduring the present cycle, a second device which is set by the firstdevice and retains its setting until the next cycle and means fortransmitting from the store signals of those information channelswhereof both associated devices are in the set state, means fortransmitting signals identifying the information channels together witha receiver, signal storage means in said receiver, means for writingreceived signals into said store, means for writing said stored signalsand means for connecting the output cyclically to a plurality ofreceivers in accordance with the identifying signals received.

4. In a multiplex transmission system a transmitter, signal storagemeans in said transmitter, means for writing signals from a plurality ofinformation channels in recurrent cycles into said storage means, meansfor reading and transmitting stored signals in the intervals between thewriting cycles, means for interrogating the signals of each informationchannel held in said store, information storage means for eachinformation channel interrogator, said information storage meansincluding a first bistable device, means for setting said device ifthere is information in the channel during the present cycle, a secondbistable device associated with each channel, means whereby said seconddevice is set by said first device when said first device is itself set,said second device being arranged to retain its setting during thefollowing cycle irrespective of the state of the first device and meansfor transmitting signals of a channel whereof both associated bistabledevices are in the set state.

5. In a multiplex transmission system a transmitter, signal storagemeans in said transmitter, means for writing signals from a plurality ofinformation channels in recurrent cycles into said storage means, meansfor interrogating the signals of each information channel stored in saidinformation channel and means for reading and transmitting from thestore those channels carrying information in the intervals betweenwriting cycles, together with a queue counter having a number of stagescorresponding to the number of transmission channels, means forinterrogating each information channel and for stepping the counter astage for each zone having information during two successive cycles andmeans whereby the counter is then stepped on through its remainingstages and pulses are fed back to activate a further information channelfor transmission in each unfilled queue counter stage, the channelsactivated being those containing information during the present frame.

References Cited by the Examiner UNITED STATES PATENTS 2,935,569 5/1960Saal et al. 179-15 2,957,949 10/1960 James et al. 179-18.9 3,084,2224/1963 Foot et al. 179-15 3,213,201 10/1965 Flood et al 17915 FOREIGNPATENTS 873,934 8/1961 Great Britain.

DAVID G. REDINBAUGH, Primary Examiner.

ROBERT L. GRIFFIN, Examiner.

1. IN A MULTIPLEX TRANSMISSION SYSTEM HAVING A SMALLER NUMBER OFTRANSMISSION CHANNELS THAN INFORMATION CHANNELS, A TRANSMITTER, SIGNALSTORAGE MEANS IN SAID TRANSMITTER, MEANS FOR WRITING SIGNALS FROM EACHOF THE INFORMATION CHANNELS INTO THE STORE IN RECURRENT CYCLES AND MEANSFOR READING FROM THE STORE INFORMATION TO BE TRANSMITTED DURING THEINTERVALS BETWEEN THE WRITING CYCLES, TOGETHER WITH CHANNEL SELECTIONMEANS INCLUDING MEANS FOR INTERROGATING EACH CHANNEL DURING WRITING, AFIRST DEVICE WHICH IS SET IF THE CHANNEL CARRIES INFORMATION DURING THEPRESENT CYCLE, A SECOND DEVICE WHICH IS SET BY THE FIRST DEVICE ANDRETAINS ITS SETTING UNTIL THE NEXT CYCLE AND MEANS FOR READING FROM THESTORE SIGNALS OF THOSE INFORMATION CHANNELS WHEREOF BOTH ASSOCIATEDDEVICES ARE IN THE SET STATE.